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sonicwave

Switzerland

http://falsig.org/simon/blog

Working as embedded developer, main specialties are: VHDL/FPGA, C/C++, low-level interfacing and communication protocols

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164
C - The %x format specifier
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18
CMake and order dependent linking of shared libraries
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13
Is it guaranteed that pthread_cond_signal will wake up a waiting thread?
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12
Jenkins pipeline sh fail with "cannot run program nohup" on windows
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11
VHDL - Incrementing Register Value on Push Button Event
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11
VHDL: creating a very slow clock pulse based on a very fast clock
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10
VHDL: How to use CLK and RESET in process
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10
pthread_cancel() function failed to terminate a thread
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9
Bool always evaluating as true
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8
16 bit std_logic_vector to lower 8 bit std_logic-vector in vhdl
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6
VHDL synthesis warning FF/Latch has a constant value of 0
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6
Compiling error opencv
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6
CMake: Embed ELF into executable
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6
How to add rt patches in linux
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5
if statement in VHDL
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5
Types unmatch VHDL code at Simulation on Modelsim, inspite of thorough check
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5
About sequential code in FPGAs
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5
Linked List - pointers
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5
My program works in ModelSim, but doesn't work on real FPGA board
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5
git workflow + preproduction
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5
pthread_create() : What is default priority and shceduling policy
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5
Proper Condition variables usage
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5
Is rising_edge in VHDL synthesizable
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5
pthread cancel is successful but failing to create thread after few 100's of thread
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5
joining the same pthread multiple times
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