Mar
18
revised terminology: how can one say a program has more data than instructions when the concept of data and instruct can't be seperated?
Hardware should be Harvard, a small typo that changes the meaning significantly
Feb
17
answered Classic RISC pipeline- what does "memory access" stage actually do?
Dec
13
awarded Critic
Dec
3
awarded Supporter
Dec
2
awarded Commentator
Dec
2
comment How branch predictor and branch target buffer co-exist?
You only want to use the value in BTB if the branch predictor says that you should predict that the branch is taken. For instance if the branch is only predicted taken for certain values of the branch history table (for a two-level adaptive predictor).
Nov
7
comment Do sse instructions consume more power/energy?
If you are sticking to one ISA (say x86 or ARM), a good metric is EPI or Energy per Instruction. A good paper on the subject by Ed Grochowski of Intel: intel.com/pressroom/kits/core2duo/pdf/epi-trends-final2.pdf
Nov
1
comment Do sse instructions consume more power/energy?
"So if I can make an app 2x faster by means of SIMD/parallelization, I've almost certainly saved power." You don't seem to be using power correctly here, you aren't saving power, you are saving energy (power*time). Energy is almost certainly what we care about here though. If it is running for an extended period of time, the frequency/voltage of the processor will scale down to reduce the power consumption, resulting in similar power levels but reduced run-time and reduced energy consumption.
Oct
23
comment How does the Control Unit in Von Neuman Model distinguish between data and instructions?
you've basically got it right with #1, but I wouldn't use the word "needs". The PC is incremented based on the instruction that just executed. If it was an add instruction, we just move to the next instruction in memory. If it was a branch, the PC gets set to something else.
Aug
20
awarded Excavator
Aug
20
revised Django view returning json without using template
data wasn't defined yet, some_data is what needed to be passed into dumps
Aug
20
comment How to find number of conflict misses in a cache simulator
Another similar solution is to just run the simulation twice, once with your normal configuration, and once with a very highly associative configuration (thousands of ways say). The capacity misses are the delta between the misses on the two configurations.
Jul
28
comment Decoding instruction using opcode and function bits
What is the Instruction Set Architecture, ARM, x86, MIPS, something else?
Apr
11
answered How does direct mapped cache work?
Aug
29
comment Why INC and ADD 1 have different performances?
@Mysticial, it doesn't particularly matter what sane compilers do, Intel spends a LOT of time trying to get fortran/cobol/assembly code that was compiled 20 years ago with crappy compilers to run faster. In many cases the source code is nowhere to be found, or the toolchains that produced the executable don't exist anymore.
Aug
23
comment Why isn't RDTSC a serializing instruction?
I changed up the example to make the second rdtsc always execute.
Aug
23
revised Why isn't RDTSC a serializing instruction?
added 60 characters in body
Aug
23
answered Allocate static memory in CPU cache in c/c++ : is it possible?
Aug
23
awarded Editor
Aug
23
revised Why isn't RDTSC a serializing instruction?
added 18 characters in body
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