Stack Exchange
log in
chat
meta
about
Stack Exchange
All Sites
Hot Questions
Top Users
Newsletters
Blogs
Jan Decaluwe
Leuven, Belgium
jandecaluwe.com
Age: 50
top
accounts
reputation
activity
favorites
subscriptions
Top Questions
6
votes
Have the errors in “HDL Chip Design” by Douglas Smith ever been corrected?
verilog
asked Feb 6 '11 at 15:06
stackoverflow.com
Top Answers
12
When should I use std_logic_vector and when should I use other data types?
stackoverflow.com
9
Where can I find a definitive list of the ModelSim error codes?
stackoverflow.com
9
How to interpret blocking vs non blocking assignments in Verilog?
stackoverflow.com
8
Ideas for a flexible/generic decoder in VHDL
stackoverflow.com
8
Datatype problem in simple IF statement in VHDL
stackoverflow.com
7
Verilog array syntax
stackoverflow.com
6
Using wire or reg with input or output in Verilog
stackoverflow.com
6
Estimating area required by a VHDL implementation
stackoverflow.com
5
How do these two modules differ in behavior
stackoverflow.com
Stack Exchange works best with JavaScript enabled
stackoverflow.com
