profile for Greg on Stack Exchange, a network of free, community-driven Q&A sites

Staff Verification Engineer with over 8 years of professional experience, plus RTL implementation and schematic experience. When I'm not resolving bugs, I'm finding ways maximize quality of the design, streamline verification, and teaching other best practices. Other skills on my tool belt: C, C++, Perl, GNUmakefile.

I am a advocate of because it gives flexibility for verification and enforces best practices for RTL design. Quality design can be done with only , however will catch basic design bugs and syntheses surprises early (e.g. transparent latches, multiple drivers on nets, procedural when intending parallel logic). #SOreadytohelp

Mission on StackOverflow (and Other StackExchange sites)

  • Help others
  • Promote best practices
  • Learn something new

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